US 7,253,123 · Granted 2007-08-07
The Nano-Coating That Shapes Every Modern Chip's Architecture
Imagine building a skyscraper where super-thin walls need to be perfectly insulated and structurally sound. This patent describes a recipe for creating those walls on computer chips using a special plasma chamber that bakes silicon-based coatings at temperatures below 450 degrees Celsius, giving them just the right electrical properties.
The plain-English version
What it protects
The claim covers a specific method for depositing silicon-based materials (like silicon carbide or nitrogen-doped variants) onto gate structures in semiconductor manufacturing using plasma-enhanced chemical vapor deposition, where the final sidewall spacer has a dielectric constant between 3.0 and 5.0 and is produced at temperatures below 450 degrees Celsius. What's protected is the combination of materials, the deposition process parameters, and the resulting electrical characteristics of the spacer layer itself.
Why it matters
Sidewall spacers are critical components in transistor architecture that control how electrical current flows through chips. By patenting a method that achieves specific electrical properties (the k-value range) while maintaining structural integrity at lower temperatures, Applied Materials locked in a manufacturing technique that enables faster, more reliable chip production without excessive heat that could damage underlying layers or require expensive cooling systems.
Real-world use
Every smartphone, laptop, and server processor made in the last 15 years likely contains transistors built using variations of this sidewall spacer technique, since controlling gate dimensions precisely is essential to making chips smaller and more powerful.
Original USPTO abstract
A method for forming sidewall spacers on a gate stack by depositing one or more layers of silicon containing materials using PECVD process(es) on a gate structure to produce a spacer having an overall k value of about 3.0 to about 5.0. The silicon containing materials may be silicon carbide, oxygen doped silicon carbide, nitrogen doped silicon carbide, carbon doped silicon nitride, nitrogen doped silicon oxycarbide, or combinations thereof. The deposition is performed in a plasma enhanced chemical vapor deposition chamber and the deposition temperature is less than 450° C. The sidewall spacers so produced provide good capacity resistance, as well as excellent structural stability and hermeticity.
Patent details
- Publication number
- US 7,253,123
- Filing date
- 2005-01-10
- Grant date
- 2007-08-07
- Assignee
- Applied Materials, Inc.
- Inventor(s)
- ARGHAVANI REZA, KWAN MICHAEL CHIU, XIA LI-QUN, YIM KANG SUB
- CPC class
- A47C4/04
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